1. Field of the Invention
This invention relates to a manufacturing method of semiconductor devices, and more particularly to a manufacturing method of semiconductor devices having lateral bipolar transistors with an SOI (Silicon on Insulator) structure, which are hereinafter referred to as BIP elements.
2. Description of the Related Art
Since lateral BIP elements formed on SOI films have a low stray capacity, they are expected to operate faster than those formed on bulk silicon substrates. Examples of such elements are disclosed in an article by J. C. Sturm et al., IEEE, EDL-8, No. 3, p. 103, 1987. A manufacturing sequence of a conventional BIP element of this type is shown in FIGS. 1A through 1D.
First, an SiO.sub.2 film 2 and a p-type SOI film 13.sub.1 are formed on an Si substrate 1. The p-type SOI film surface undergoes the implantation of boron ions and annealing to convert the surface layer of the p-type SOI film 13.sub.1 into a p-type high-concentration impurity layer (p.sup.+ -type layer). In this way, the p-type impurity layer (p-type layer)13.sub.2 and p.sup.+ -type layer 13.sub.3 are formed. After a CVD oxide film is deposited on the p.sup.+ -type layer 13.sub.3 to form a resist film pattern 15.sub.1 that covers a predetermined region of the CVD oxide film, with the resist film pattern 15.sub.1 as mask, the CVD oxide film is selectively etched to form a CVD oxide film pattern 14.sub.1. (FIG. 1A)
Then, with the resist film pattern 15.sub.1 as mask, the exposed p.sup.+ -type layer 13.sub.3 is etched to form a p.sup.+ -type region 13.sub.5. The p-type layer 132 is also partly etched in the direction of thickness. After the resist film 15.sub.1 is removed, another resist pattern 15.sub.2 is formed on the CVD oxide film pattern 14.sub.1 and a predetermined region of the p-type layer 13.sub.2. By using the resist pattern 15.sub.2 as mask, the p-type layer 132 undergoes selective etching to form an island p-type region 13.sub.6. (FIG. 1B)
After the resist pattern 15.sub.2 is removed, by using the CVD oxide film pattern 14.sub.1 as blocking mask, the p-type region 13.sub.6 undergoes the ion implantation of n-type impurities such as arsenic ion and annealing, which forms an n-type high-concentration impurity region (hereinafter, referred to as an n.sup.+ -type region) 17, an n.sup.+ -type region 18, and a p-type region 13 that is the remaining portion of the p-type region 13.sub.6. (FIG. 1C)
After an interlayer insulating film 111 is deposited and necessary contact holes are made therethrough, interconnections 10 are formed which each make ohmic contact with the individual impurity regions. Then, a passivation film 11.sub.2 is formed to complete an n-p-n lateral BIP element. Here, the emitter portion is indicated by E, the base portion by B, and the collector portion by C. In the BIP element, the p-type region 13 is an internal base region and the p.sup.+ -type region 135 is an external base region. An n.sup.+ -type region 17 that meets the left side of the internal base region 13 is the emitter region and an n.sup.+ -type region 18 that meets the right side of the internal base region 13 is the collector region. (FIG. 1D)
The SOI lateral BIP element produced by the aforementioned method, however, does not provide high performance as expected because of the following problems: first, the withstand voltage decreases significantly, and second, the long transit time of carriers in the base region impairs the high-frequency characteristics, such as cut-off frequency.
The cause of the decreased withstand voltage lies in the fact that a high electric field is apt to develop at the junction between the base region and the collector region. More specifically, when ion implantation is performed on the p-type region 13.sub.6, the sidewalls of the p.sup.+ -type region 13.sub.5 and p-type region 13.sub.6 are also liable to be affected by doping of the n-type impurities. This also forms the highly doped n.sup.+ -type regions 17.sub.2 and 18.sub.2 on the sidewalls as shown in FIG. 2, which creates a highly doped p-n junction with respect to the external base region 13.sub.5. With the base-collector junction applied with the reverse bias, formation of such a highly doped p-n junction decreases the base-collector withstand voltage.
The long transit time of carriers in the base region is ascribed to the uniformity of the impurity concentration profile parallel with the substrate surface in the base region, which results in the poor transport factor of carriers in the base region. The poor transport factor results from the fact that with the above-described method, it is impossible to give a desired impurity concentration profile to the p-type region 13 of the base region because of its structure.